Data buses are used in integrated circuits (ICs) to transfer data between termination devices within the IC. Usually, one or more of the termination devices is, or is coupled to, a user-controlled device such as a microprocessor and operates as a control device. Another termination device is, or is coupled to, a peripheral device, such as an on-chip or off-chip memory or the like, and operates as a controlled device. For example, an IC might include a microprocessor coupled through a main bus to a bus slave that operates or controls a peripheral controller and/or peripheral device. If the peripheral device is an off-chip device, such as an off-chip memory, the peripheral controller may be on the same chip as the bus slave, and a peripheral bus provides control and data communications between the off-chip peripheral device and the on-chip peripheral controller.
Ordinarily, a single peripheral device is controlled by a single controller through a peripheral bus. Consequently, the peripheral controller is often included on the same IC chip as the bus slave. If it is desired to add a second termination device to control the peripheral device, it may be accomplished by adding another IC chip containing the second termination device (bus slave, for example) and a second peripheral controller. Under such circumstances, the second peripheral controller would also coupled to the peripheral bus. Thus, an off-chip memory would be coupled by a peripheral bus to several peripheral controllers on different IC chips, each peripheral controller being coupled to a different master device, such as through a respective bus slave and main bus. To avoid conflict between the plural peripheral controllers' operation of the peripheral device, it is necessary to arbitrate use of the peripheral bus among the several peripheral controllers, allowing one or another peripheral controller access to the peripheral bus.
It might be possible to accommodate plural master devices through a modification of a single peripheral controller. However, modification of the peripheral controller increases the risk of timing conflicts. Moreover, if the peripheral controller is of a standard, verified design, modification of a peripheral controller requires re-verification, a time-consuming process.
There is a need for an system that permits communication between plural master devices and a peripheral device without modification of the peripheral controller and for a system that arbitrates use of the peripheral device among the plural peripheral controllers.